This invention is related generally to reduced power logic and more specifically to reduced power logic having full voltage output swing and operating with recycled energy.
A previous application, U.S. patent application Ser. No. 09/967,189, entitled RESONANT LOGIC AND THE IMPLEMENTATION OF LOW POWER DIGITAL INTEGRATED CIRCUITS, disclosed a logic system operating with recycled energy. The logic disclosed therein included several logic gates each having a discharge path 10 and a precharge path 12 as shown in FIG. 1. The discharge path 10 and precharge path 12 are connected in parallel between a clock line 14 and an output node 16, having load capacitance, CL18. The discharge path 10 is generally a logic circuit stage that implements a logic function, such as an inverter gate, NAND gate, as shown in FIG. 2A, or NOR gate (not shown), or part of a more complex logic function. A conductive path is developed between the output node and the clock line depending on the state of one or more inputs to the logic circuit stage during an evaluation period or phase. Thus, the discharge path 10 is conditionally conductive.
The precharge path 12, also connected between the output node 16 and the clock line 14, develops a conductive path, unconditionally, during a precharge phase or period. During this phase, the output node 16 is precharged to a voltage level related to the voltage level achieved by the clock line, which is a logic high during the precharge phase.
During the evaluation phase, the precharge path 12 is not conductive and during the precharge phase, the discharge path 10 is not conductive. Thus, in operation after the output node 16 is charged during the precharge phase, the logic function is evaluated during the evaluation phase, using the charge on the output node 16. If the inputs are such that the logic circuit stage is not conductive, then the output node 16 stays charged at the voltage level to which it was precharged. If the inputs are such that the logic circuit stage is conductive, then the output node 16 is discharged to approximately the low potential of the clock signal 14.
In the previous application, the precharge path 12 is implemented as a diode, as shown in FIG. 2B. The diode implementation however creates a problem, in that the output node 16 cannot be precharged to a voltage substantially equal to the high voltage of the clock signal 14. This limits the voltage output of the output node 16 and has effects on circuitry that receives the less-than-full swing output from the logic circuit stage. One such effect is reduced drive to subsequent logic inputs if the circuit is operated at high clock rates, thereby reducing the maximum clock rate of such circuitry.
Therefore, there is a need the output of the logic circuit stage to achieve voltage levels substantially equal to the voltage levels of the clock signal carried on the clock line to which the logic circuit stage is connected.
The present invention is directed towards the above need. The present invention, in accordance with one embodiment of the present invention, includes a discharge path, a precharge path and a control circuit. The discharge path is connected between a clock line and an output node and includes one or more transistors configured to evaluate a logic function of at least one input during an evaluation phase. The precharge path is connected between the clock line and the output node, and includes a PMOS transistor having a gate and a channel between a source and drain region of the transistor, the drain being connected to the output node and the source being connected to the clock line. The control circuit has an output connected to the gate of the precharge path transistor and is configured to maintain a source-to-gate voltage on the precharge path transistor such that, independent of the states of the inputs and the output node, the channel of the precharge transistor provides a conductive path between the clock line during a precharge phase.
The clock line of the present invention is connected to a clock circuit that captures, on the clock line, energy from the output node via the discharge path and provides a portion of the captured energy back to the output node via the precharge path.
A method in accordance with one embodiment of the present invention includes the steps of disabling the precharge path during a first voltage of the clock signal by providing the first voltage to the source of the PMOS transistor and enabling the precharge path during a second voltage of the clock signal by providing the second voltage to the source of the PMOS transistor and providing to a gate of the PMOS transistor a voltage having a range of approximately a NMOS transistor threshold voltage above the first voltage of the clock line to one PMOS transistor threshold voltage below the second voltage of the clock line.
An advantage of the present invention is that the voltage range of the output node is approximately equal to the voltage range of the clock line, which is approximately a range from zero volts to the positive supply voltage.
Another advantage is that the output node can drive more logic inputs at a given clock cycle rate.
Yet another advantage is that the logic circuitry can operate at a higher clock cycle rate.
Yet another advantage is that lower power operation is achieved by removing a direct path between the output node and the clock line that consumes power during switching.
Yet another advantage is that low power operation is achieved because a portion of the energy used to precharge the output node and operate the discharge path is returned to the output node by the clock circuit.